1. Field of the Invention
The present invention relates to a method for designing a semiconductor integrated circuit and an apparatus for supporting a design of thereof.
2. Description of Related Art
Recently, the wide use of battery-driven products, such as a portable music player and a mobile phone, has spread. The products are provided with a semiconductor integrated circuit. As a result, there is ever increasing a demand for semiconductor integrated circuits that can consume less power. As a method to reduce power consumption of the semiconductor integrated circuit, a method of reducing power supply voltage has been known. When the power supply voltage is reduced, current flowing in an internal circuit is generally also reduced, while additionally making it possible to suppress a generation of noise. In recent years, however, as the speed of the semiconductor integrated circuit increases, the current amount may not be reduced only by reducing the power supply voltage and a generation amount of noise may not be reduced regardless of reducing the power supply voltage.
When the power supply voltage is reduced without reducing the power noise, an occupying rate of the power noise with respect to the power supply voltage is relatively large. At this time, a temporal fluctuation (hereinafter, referred to as a jitter) in a phase of an internal signal of the semiconductor integrated circuit is increased due to the power noise. A method of reducing a jitter due to the generation of power noise of the semiconductor integrated circuit has been known (for example, see Non-Patent Document 1).
FIG. 1 is a flow chart illustrating a delay calculation in consideration of SI (Signal Integrity) described in Non-Patent Document 1 and timing verification. A flow chart illustrated in FIG. 1 includes three processing steps.
A first processing step performs a delay calculation (step S3) in consideration of IR drop based on a parasitic parameter 101 obtained from a highly-accurate parasitic parameter extraction (step S1) and IR drop information 103 obtained from a highly-accurate IR drop analysis (step S2), thereby outputting first delay information 104. IR drop means that a voltage on a power source at a portion of a chip drops due to the influence of a wiring resistance. By using the information, a static timing analysis (step S4) is performed and a timing relationship between all the signal lines and a signal line that may be a noise source is extracted and output as timing information 102.
A second processing step performs a delay calculation (step S5) in consideration of crosstalk between the parasitic parameter 101 and the timing information 102 and outputs, as delay calculation results of a network affected by the crosstalk, second delay information 105 that is information different from the first delay information 104.
A third processing step performs a static timing verification (step S6) based on the first delay information 104 and the second delay information 105 that is information different from the first delay information 104 to determine whether timing is converged (step S7). By a series of sequences as described above, the timing convergence is completed by performing the timing verification while considering both the IR drop and the crosstalk (step S8).
[Non-Patent Document 1] “Method For Converging Timing In Consideration Of Signal Integrity” OKI Technical View No. 196, Vol. 70, No. 4, p. 50 to 51 (October, 2003)